NULL need not be all bits 0
D. Hugh Redelmeier
hugh@mimosa.com
Tue, 26 Oct 1999 11:05:16 -0400 (EDT)
| From: Werner Koch <wk@gnupg.org>
[about machines on which a NULL pointer representation does not have
all bits 0]
| > I have used such a machine (but they are rare).
|
| I am curious: What kind of machines are this.
The machine was a CDC Cyber something-or-other. This was not the
traditional CDC 60-bit architecture of the 6600, but a newer 64-bit one
(it did have a switch to run the old code). It had a segmented address
space and "rings" of protection, as in MULTICS.
Each pointer was 64 bits, and included the segment and ring number.
If I remember correctly, ring 0 was the highest level of protection
(this, in fact, is the MULTICS terminology). Loading 0 into an
address register from user code caused a trap for protection
violation. So you didn't want this to be the representation for NULL.
My impression of this machine was that it was the opposite of what
made CDC great. It wasn't fast because it was complicated. Its
design slightly predated the great wave of RISC thinking. I was
involved in an optimizing C compiler project that targeted it around
1985 or so.
I've never looked closely enough at other segmented architectures for
this feature. If I designed one, without thinking of C code, I'd have
the hardware process addresses upon loading a pointer register rather
than waiting until the address is used. There is a lot of processing
to do (fetching segment descriptors etc.) and this would create the
maximum overlap. This overlap would probably be critical to hiding
the overhead of a segmented architecture, allowing it to be
competitive.
I think the C implementation on the traditional Burroughs architecture
throws up its hands and implements (most? all?) C data in One Big
Array. This, of course, throws away the beauty of that architecture.
Somehow I imagine that the Intel 286 architecture survives all-zero
"far" pointers. Otherwise the screams would have deafened us.
Clearly this is true in 8086 mode, where the segment registers just
hold integers-that-are-multiples-of-16, but I infer it must be true in
the full-blown-segment mode too. Or at least the OS can arrange for
it to be true.
The C committee was aware of these issues and took them into account.
Hugh Redelmeier
hugh@mimosa.com voice: +1 416 482-8253